Call for Papers

IEEE Joint Conference ICICDT-2016 & 4S-2016

Ho Chi Minh City, Vietnam

27th – 29th June, 2016


Welcome to the 4th Solid State Systems Symposium – VLSIs and Semiconductor Related Technologies (4S-2016). This is an event organized every two years and aimed to be a meeting place, a discussion forum for scientists, engineers and students all over the world, who are interested in VLSI and semiconductor – related technologies.

The 4S-2016 symposium is joined with the International Conference on Integrated Circuit Design and Technology (ICICDT-2016) to form the “IEEE Joint Conference ICICDT-2016 & 4S-2016”.

The conference in 2016 is an activity to promote the “HCMC Program of Semiconductor Industry Development 2013 – 2020”. This conference will be jointly organized by Vietnam National University HCMC (VNU-HCM), Department of Information and Communications HCMC and Institute of Electrical and Electronics Engineers (IEEE) in three days, from June 27th to June 29th, 2016, in Ho Chi Minh City, Viet Nam.

Integrated circuit (IC) engineering has traditionally been separated along the boundary between design and process technology. As IC products advance toward higher performance and better energy efficiency while the time to market continues to shorten, future IC engineers will need a deeper understanding of the interrelation between design and process technology to widen the product optimization window.

The 4th Solid State Systems Symposium – VLSIs and Semiconductor Related Technologies (4S-2016) is the forum for engineers, researchers, graduate students and professors to cross the design-technology boundary through interactions with experts in design and process technology to develop the over skill for future IC research and development.


ICICDT-2016 & 4S-2016 Venue

Hotel Majestic Saigon: 1 Dong Khoi Street, Ben Nghe ward, District 1, Ho Chi Minh City, Vietnam.

(Location and map)

Original papers are solicited in the following subject areas:

  • Advanced materials and processing technologies
  • Advanced transistor and interconnect structures
  • Three-dimensional (3D) integration
  • Variation-tolerant designs
  • Process and design techniques for soft errors, plasma-induced damage, and reliability
  • Advanced memory devices and circuits
  • RF, analog, mixed signal, and I/O circuits for future technology generations
  • Simulation and modeling of advanced processes, devices, and circuits
  • EDA and design optimizations across system, circuit, and/or device levels for high performance, energy efficiency, yield, and/or reliability
  • Design for manufacturing, yield, and test
  • System-on-Chip (SoC) and system-in-package (SiP) design integration
  • Power semiconductor technologies and circuits
  • Emerging technologies and circuits