Monday, June 27th, 2016 (Hotel Majestic Saigon)
|9:30AM–10:30AM||Tutorial 1: “Circuit and Device Interactions for Nonvolatile Memory in IoT Era”||Prof. Meng-Fan (Marvin) CHANG, National Tsing Hua University (NTHU), Taiwan||Serenade room|
|11:00AM–12:00PM||Tutorial 2: “Technology trends and applications of embedded STT-MRAM from big data to wearable devices”||Dr. Shinobu Fujita, Toshiba Corp., Japan||Serenade room|
|1:30PM–2:30PM||Tutorial 3: “Reliability Physics of SiO2 and High-k Dielectric Films for CMOS, RF, and Power Devices”||Dr. Kenji Okada, TowerJazz Panasonic Semiconductor (TPSCo), Japan||Serenade room|
|3:00PM-4:00PM||Tutorial 4: “Technologies for developing a successful IoT MCU chip”||Mr. Lei (Jerry) Zhang||Serenade room|
Please click this link to download a detailed Conference program (as of 22 June 2016).
Tuesday, June 28th, 2016 (Hotel Majestic Saigon)
|8:00–8:30AM||Opening remarks||Dang Luong Mo|
|8:30–9:15AM||Keynote 1: Uming Ko, MediaTek|
|9:15–9:55AM||Session A: Low-Power Circuits & Technology||Tran Xuan Tu|
|10:10–10:50AM||Session B: Reliability and Soft Error||Koji Eriguchi and Yuichiro Mitani|
|10:50–11:10AM||Session C: I/O Circuits and ESD Protection||Lorenzo Cerati and Philippe Galy|
|11:10AM–12:10PM||Workshop A, B & C|
|1:05–1:50PM||Keynote 2: Yoshikazu Nitta, Sony Corporation|
|1:50–3:00PM||Session D: Advanced Transistors/Materials and High Power/High Voltage||Bich-Yen Nguyen and Wenke Weinreich|
|3:15–4:15PM||Session E: RF&Analog Mixed Signal||Cuong Huynh and Dina Triyoso|
|4:15–5:15PM||Workshop D & E|
|6:30–8:00PM||Dinner Reception at Hotel Majestic Saigon|
Wednesday, June 29th, 2016 (Hotel Majestic Saigon)
|8:00–8:15AM||Opening remarks||Yuichiro Mitani|
|8:15–9:00AM||Keynote 3: Tran Thang, Synopsys|
|9:00–10:10AM||Session F: SoC/MPSoC/SIP & CAD/DFX||Dac Pham, Juergen Pille, and Rouwaida Kanj|
|10:30–11:20AM||Session G: Advanced Memory Devices||Hideto Hidaka|
|11:20AM–12:20PM||Workshop F & G|
|1:20–2:05PM||Keynote 4: Sommawan Khumpuang, AIST|
|2:05–2:35PM||Session H: Minimal Fab Application||Dang Luong Mo and Sommawan Khumpuang|
|2:55–3:55PM||Session I: 3D Integration & Emerging Technologies||Thomas Ernst and Thuy Dao|
|3:55–4:55PM||Workshop H & I|
|4:55–5:10PM||Best student paper award|
|5:10–5:25PM||Closing Remarks & Presentation of ICICDT 2017|
|6:00–8:00PM||Post Conference Meeting for TPC|
Prof. Meng-Fan (Marvin) CHANG, National Tsing Hua University (NTHU), Taiwan
Memory has become one of the bottlenecks in the development of IoT and wearable devices with low energy consumption. This tutorial addresses trends in the development of nonvolatile memory (NVM) for energy-efficient IoT applications. We will examine a variety of NVM technologies, including Flash, resistive RAM (ReRAM), and phase-change memory (PCM). This tutorial will explore the challenges faced by researchers in the device and circuit interactions for nonvolatile memory. We will also look at some state-of-the-art silicon-verified device-circuit integration techniques, including high-speed, low-power and endurance-extention NVM macros. The requirement and implementation of NVM devices beyond conventional applications, such as nonvolatile-logics (nvLogics) for nonvolatile processors, will also be discussed.
Meng-Fan Chang is a full Professor in the Dept. of Electrical Engineering of National Tsing Hua University (NTHU), Taiwan. Since 2011, he has also served as the Associate Executive Director of National Program for Intelligent Electronics (NPIE) in Taiwan during 2011-2016. Dr. Change obtained considerable practical experience before joining NTHU in 2006, having spent more than ten years working in industry.
Between 1997 and 2006, Dr. Chang worked in the development of SRAM/ROM/Flash macros/compilers at Mentor Graphics (New Jersey, US), TSMC (Taiwan), and the Intellectual Property Library Company (Taiwan). He has been service as an associate editor for IEEE TVLSI, IEEE TCAD and IEICE Electronics. He has been serving on technical program committees for ISSCC, IEDM, A-SSCC, ISCAS, and numerous international conferences. His research interests include circuit design for volatile and nonvolatile memory, 3D-Memory, spintronics and memristor logics, computing-in-memory, and circuit-device-interactions in non-CMOS devices.
Dr. Shinobu Fujita, Toshiba Corp., Japan
Recently, advanced embedded STT-MRAM technologies expected for high-speed and low-power embedded memory applications have been mature. Advancement of embedded STT-MRAM technologies will be overviewed to clarify their advantageous features such as a high-speed access, a novel scalability and normally-off + instant-on mode. Then, various applications from big data to wearable and IoT devices will be presented, and issues regarding their applications will also be addressed. Furthermore, future challenges regarding technologies and application will be analyzed.
Shinobu Fujita took PhD of University of Tokyo in 1989. He joined Toshiba in 1989. He has been working for new applications based on nonvolatile memory for over 10 years. Currently, he is a Chief Research Scientist of Toshiba Corporate R&D Center and leading a project for development of embedded STT-MRAM cache systems based on Normally-off Computing.
for CMOS, RF, and Power Devices”
Dr. Kenji Okada, TowerJazz Panasonic Semiconductor (TPSCo), Japan
Reliability has been regarded as the showstopper of various kinds of state-of-the-art devices. To achieve further advance of these devices, both reliability and device performance must be well balanced and kept at the extremely high levels. This is valid not only for the extremely scaled CMOS devices, but also for various power and RF/MMIC devices processed on Si, GaN, GaAs, SiC and so on. For this purpose, deeper understandings on the physics of various reliability items such as TDDB, SILC, NBTI, PBTI, and HC are crucial as well as that on the device performance.
Therefore, in this tutorial, reliability physics will be discussed with focusing on the dielectric films used as the gate dielectrics, tunnel dielectrics, capacitor films, and so on in each device. Thickness of dielectrics discussed in this tutorial is very wide, from ~1.5 to ~40 nm. This tutorial discusses dielectric films developed for devices in the following opposite directions:
(1) EOT scaling of gate dielectrics in CMOS ‘system LSI’ devices (~1.5 to ~10 nm), and,
(2) very thick SiO2-base and Si3N4-base dielectric films (~10 to ~40 nm) used in power and RF/MMIC devices and also used as inter-metal dielectrics (IMD).
As for the EOT scaling direction (1), mechanisms and models for various reliability items will be discussed, followed by the discussions on the alteration of models due to the scaling and to the introduction of new materials such as metal gate electrode and high-k gate dielectrics. For example, with the thinning of gate dielectrics, the soft breakdown, which we reported for the first time as the ‘B-mode SILC’ and ‘B-mode shift’, becomes observable even by conventional measurements. Appearance of soft breakdown strongly required us to change the lifetime prediction method. Furthermore, the introduction of high-k materials to the gate stack structure required us to take into account the existence of high density initial traps. High density initial traps let us misunderstand the TDDB statistics and also increased the importance of BTI degradation.
As for the very thick dielectric films (2), anomalous TDDB statistics which prevents us from appropriately predicting the lifetime with conventional methods will be discussed with SiO2-base gate dielectrics and Si3N4 films in MIM capacitors. The cause of this anomalous TDDB statistics is just an intrinsic and simple event, that is, the carrier charging into initial and stress-generated traps and, hence, no one can free from this anomalous TDDB statistics regardless of the material. Impact of this charging-induced dynamic stress relaxation (CiDSR) effect on various parameters in TDDB statistics will be demonstrated.
Kenji Okada received the B.S. and the M.S. degrees in the materials science from Osaka University, Osaka, Japan, in 1985 and 1987, respectively. He joined the Semiconductor Research Center, Matsushita Electric Industrial Co., Ltd (Panasonic Corporation), Osaka, Japan, in 1987. He had been engaged in the research and developments of the gate and tunnel dielectrics used in Si MOS and flash memory devices, and received the Ph.D. from Osaka University, Osaka, Japan, in 2003. From 2004 to 2007, he was with the Millennium Research for Advanced Information Technology (MIRAI) project, Tsukuba, Japan, and investigated the reliability physics of high-k stacked gate dielectrics such as TDDB, NBTI, and PBTI. From 2008 to 2013, he engaged in the research and development of various advanced devices at Panasonic, such as Si system LSI with high-k/metal gate, CMOS and CCD image sensors, power devices including GaN and SiC from the viewpoint of device reliabilities as a manager of reliability development team. Since 2014, he has been with Process Technology Center, TowerJazz Panasonic Semiconductor Co., Ltd. (TPSCo), where he continues his investigation on the reliability physics of various devices. He served on the technical committees of IEEE Semiconductor Interface Specialists Conference (SISC, 2000~2002), IEEE International Electron Devices Meeting (IEDM, 2001~2002 and 2010~2011), IEEE International Reliability Physics Symposium (IRPS, 2003, 2006, 2007, and 2016), and so on. He also served as an editor of Japanese Journal of Applied Physics (JJAP) from 2000 to 2008. Dr. Okada is a member of the Japan Society of Applied Physics and also of the IEEE Electron Device Society and Reliability Society.
Mr. Lei (Jerry) Zhang
MCU as the terminal of IoT or indispensable component in the server, which request higher capability on connectivity, with lowest power consumption for portable application. This tutorial will give an overview of technologies widely used in MCU chip design and integration. It will illustrate several topics, the approaches to lower down dynamic and static power consumptions via process, architecture and synthesis; the signal integrities of analog and RF IPs; the IO concerning for high performance EMC compliant; and general security protection methods in the chip. A practicable developing flow also been introduced to demonstrate the real engineering works behind a chip.
Lei Zhang achieved a Master Degree in NanYang Tech. Univ. and MBA in Xi’an JiaoTong University.
He has been a Senior SoC design Manager in NXP (Previous Freescale) Semiconductor Micro- Group since 2011. He is focus on MCU architecture and RTL2GDS chip developing. He leads the team built 11 dice in ARM Based Kinetis family and four new generation 8-Bits products on different technic notes. 50% of them were successfully goes to mass production with only one Tape-Out.
From 1998 to 2011, he worked in Infineon Technologies Automotive and Industry Group, as a technical lead and design manager, focus on 32bit-Tricore and 8/16-Bits MCU develop. He accumulate abundant skill on circuit design, top-level integration, timing closure, verification and DFT. He also worked in China Academic of Science on Analog circuit design for four years from 1994.
He has several publications in EDA and IEEE conference on Signal Integrity for timing and power analysis, as well as chip level Dynamic Frequency & Power Management. He holds patents in digital and analog circuit design area. He also got certificate of Infineon Project Manager Academic Assessment. And he has ever been the Lecturer of Xi’an JiaoTong University in EE Department.